1.Responsible for high performance block implementation (RTL to GDSII);
2.Perform block level floor planning,power grid implementation,APR placement,timing optimization,CTS and routing;
3.Close the design to meet timing,power budget and area targets;
4.Run physical verification flows (DRC/LVS/EM/IR),implement fixes to meet the requirements;
5.Implement ECO's to address functional bugs,timing and physical verification violations;
6.Responsible for generation and maintenance of block level STA constraints and perform STA signoff checks;
7.Responsible for timing model generation and support successful integration of blocks into SOC.

1.Master's/Bachelor's degree in Electrical Engineering with an emphasis in IC design;
2.Hands-on experience (Final year or graduate school project) in digital physical design is a plus;
3.Knowledge in Synopsys implementation tools (DC,ICC2),Cadence (Innovus) implementation tools is a plus;
4.Fundamental knowledge in semiconductor process is preferred;
5.Proficient in TCL coding,Perl/Python knowledge is a plus;
6.Good written and communication skills.