1.Responsible for fully customized layout design of Finfet process high-performance IP;
2.Perform block level layout. Conduct physical verification (DRC and LVS using Mentor tools);
3.Team work with analog designers, optimize layout;
4.Perform floor planning and placements (pad locations and custom routing).

1.Bachelor degree or above in electronics and computer related majors;
2. Proficient in using EDA tools such as Virtuoso/Laker/Calibre/StarRC;
3.Experience in IP layout design such as STD cell/SRAM/IO/Analog under Finfet process is preferred;
4.Programming languages such as SKILL/Perl/TCL are preferred;
5. Have good communication skills, logical analysis skills, and teamwork skills;
6. Strong sense of responsibility and strong ability to withstand pressure.